Introduction
NEC Electronics has introduced an advanced 55-nanometer (nm) eDRAM technology to the ASIC industry. NEC has been the leader in performance and volume delivery of embedded DRAM (eDRAM).
This new eDRAM family has various features:
- Random access time an order of magnitude shorter than competitor offerings
- Fully CMOS-compatible process using a single fab and few extra masks to minimize cost
- SRAM-like access for easy integration with existing intellectual property (IP)
- SoC-friendly macros that simplify integration, with orientation in any direction and over-the-top routing
- The latest 55 nm family, which adds significant process enhancements to the improved materials that have proven so successful in our previous 90 nm family
These eDRAMs have grown into popularity for a variety of applications, including communications systems to home electronics, from enterprise servers to entertainment systems. NEC Electronics has shipped high volumes of ASICs with eDRAM for all of these application areas.
The advantages of NEC Electronics' broad experience with eDRAM applications are being seen by ASIC designers, with the benefits of embedded DRAM in chip after chip.
Same is the experience the latest generation of NEC products.
To achieve fast access times while keeping power consumption surprisingly low, this 55 nm technology leverages process enhancements. It makes this eDRAM ideal for portable applications such as mobile phones.
There are various advantages of embedding large blocks of DRAM into the ASIC.
The eDRAM boosts memory performance and overall system bandwidth by eliminating the need to drive I/O signals to separate memory chips. Power consumption and noise can also be reduced by eliminating the I/O drivers. Board layouts can be simplified by a smaller package and reduced component count which allows shrinking the size of the board.
There are various unique advantages of eDRAM fulfilled by NEC Electronics. Designers always get full CMOS performance and reliability as NEC’s eDRAM technology is fully compatible with its standard and fully qualified CMOS process. Any CMOS IP can coexist on the same chip with eDRAM. Costs are kept reasonable as integrating eDRAM requires few additional process steps.
Parasitic resistance and capacitance is dramatically reduced by the advanced structure, throughout the memory array, which minimizes both random access time and power consumption. As required for today's CMOS logic, the low parasitic also ensure stable operation under low operating voltage.
Click here to order EDRAM ASICs- Application Specific Integrated Circuit samples from NEC Electronics America.
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